This patent claims the benefit of U.S. Prov. No. 61/723,470 filed Nov. 7, 2012, the disclosure of which is hereby incorporated by reference.
In advanced technology nodes of integrated circuit industry, high k dielectric material and metal are adopted to form a gate stack of a field-effect transistor (FET) such as a metal-oxide-semiconductor field-effect transistors (MOSFETs). Metal gate stacks are often planarized, such as by chemical-mechanical polishing (CMP), and it is common to have the resulting gate height after CMP be relatively short. This can result in undesired consequences, such as increased defects (e.g., hump defects) and poor on/off (Ion/Ioff) device performance. Therefore, a structure of a metal gate stack and a method making the same are needed to address the issues identified above.